2018-04-05

SOC/ASIC Verification Engineer

Posted on Apr 5

Location: Santa Clara, CA
Job Type: Full Time
Job ID: W4156869

Job Title: SOC/ASIC Verification Engineer
Location: Santa Clara, CA
Job Type: Full Time
 
Job Description:
  • Verification Leads who has owned verification for IP or SoC for ASIC Implementation with multiple clock domains, power domains and have good knowledge in SV and constrained random methodologies
  • System Verilog & OVM/UVM/VMM Methodologies, C Based Verification, Low Power Verification, Gate Simulations, Coverage based Constrained Random Verification, Assertions
  • Own and execute verification at SoC or sub-system or IP level.
  • Understanding SoC/Sub-system/IP architecture/use cases and develop Test plans and Verification Plans
  • Architecting Testbench environment to cover all scenarios required to meet First Pass Si Success
  • Ensure reuse for better productivity and meet critical deadlines
  • Develop Test bench and environment from scratch including flows
  • Lead Experience for team of 12+ verification engineers for atleast 2 projects
  • Understanding of FPGA/Post-Si Validation platform to have a better support
  • Code and Execute tests and support regression, coverage coding and coverage analysis
  • Monitor, control tests execution, reviews, defect tracking and on time
  
Primary Skills:
  • ASIC/SOC Verification, System Verilog & OVM/UVM/VMM Methodologies, C Based Verification, Low Power Verification, Gate Simulations, Coverage based Constrained Random Verification, Assertions
 
Secondary Skills:
  • Understanding of FPGA/Post-Si Validation platform to have a better support
 
Educational Qualifications
  • BE ( Telecom/electronics)
 
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